Datasheet

V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER)
R01UH0015EJ0300 Rev.3.00 Page 623 of 870
Sep 30, 2010
18.7 DMA Channel Priorities
The DMA channel priorities are fixed as follows.
DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3
The priorities are checked for every transfer cycle.
18.8 Time Related to DMA Transfer
The time required to respond to a DMA request, and the minimum number of clocks required for DMA transfer are
shown below.
Single transfer: DMA response time (<1>) + Transfer source memory access (<2>) + 1
Note 1
+ Transfer destination
memory access (<2>)
DMA Cycle Minimum Number of Execution Clocks
<1> DMA request response time 4 clocks (MIN.) + Noise elimination time
Note 2
External memory access Depends on connected memory.
Internal RAM access 2 clocks
Note 3
<2> Memory access
Peripheral I/O register access 3 clocks + Number of wait cycles specified by VSWC register
Note 4
Notes 1. One clock is always inserted between a read cycle and a write cycle in DMA transfer.
2. If an external interrupt (INTPn) is specified as the trigger to start DMA transfer, noise elimination time is
added (n = 0 to 7).
3. Two clocks are required for a DMA cycle.
4. More wait cycles are necessary for accessing a specific peripheral I/O register (for details, see 3.4.8 (2)).