Datasheet

V850ES/JG3 CHAPTER 3 CPU FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 47 of 870
Sep 30, 2010
3.4.6 Peripheral I/O registers
(1/10)
Manipulatable Bits Address Function Register Name Symbol R/W
1 8 16
Default Value
FFFFF004H Port DL register PDL
√
0000H
Note
FFFFF004H Port DL register L PDLL
√ √
00H
Note
FFFFF005H Port DL register H PDLH
√ √
00H
Note
FFFFF006H Port DH register PDH
√ √
00H
Note
FFFFF00AH Port CT register PCT
√ √
00H
Note
FFFFF00CH Port CM register PCM
√ √
00H
Note
FFFFF024H Port DL mode register PMDL
√
FFFFH
FFFFF024H Port DL mode register L PMDLL
√ √
FFH
FFFFF025H Port DL mode register H PMDLH
√ √
FFH
FFFFF026H Port DH mode register PMDH
√ √
FFH
FFFFF02AH Port CT mode register PMCT
√ √
FFH
FFFFF02CH Port CM mode register PMCM
√ √
FFH
FFFFF044H Port DL mode control register PMCDL
√
0000H
FFFFF044H Port DL mode control register L PMCDLL
√ √
00H
FFFFF045H Port DL mode control register H PMCDLH
√ √
00H
FFFFF046H Port DH mode control register PMCDH
√ √
00H
FFFFF04AH Port CT mode control register PMCCT
√ √
00H
FFFFF04CH Port CM mode control register PMCCM
√ √
00H
FFFFF066H Bus size configuration register BSC
√
5555H
FFFFF06EH System wait control register VSWC
√
77H
FFFFF080H DMA source address register 0L DSA0L
√
Undefined
FFFFF082H DMA source address register 0H DSA0H
√
Undefined
FFFFF084H DMA destination address register 0L DDA0L
√
Undefined
FFFFF086H DMA destination address register 0H DDA0H
√
Undefined
FFFFF088H DMA source address register 1L DSA1L
√
Undefined
FFFFF08AH DMA source address register 1H DSA1H
√
Undefined
FFFFF08CH DMA destination address register 1L DDA1L
√
Undefined
FFFFF08EH DMA destination address register 1H DDA1H
√
Undefined
FFFFF090H DMA source address register 2L DSA2L
√
Undefined
FFFFF092H DMA source address register 2H DSA2H
√
Undefined
FFFFF094H DMA destination address register 2L DDA2L
√
Undefined
FFFFF096H DMA destination address register 2H DDA2H
√
Undefined
FFFFF098H DMA source address register 3L DSA3L
√
Undefined
FFFFF09AH DMA source address register 3H DSA3H
√
Undefined
FFFFF09CH DMA destination address register 3L DDA3L
√
Undefined
FFFFF09EH DMA destination address register 3H DDA3H
√
Undefined
FFFFF0C0H DMA transfer count register 0 DBC0
√
Undefined
FFFFF0C2H DMA transfer count register 1 DBC1
√
Undefined
FFFFF0C4H DMA transfer count register 2 DBC2
√
Undefined
FFFFF0C6H DMA transfer count register 3 DBC3
√
Undefined
FFFFF0D0H DMA addressing control register 0 DADC0
R/W
√
0000H
Note The output latch is 00H or 0000H. When these registers are in the input mode, the pin statuses are read.