Datasheet

V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER)
R01UH0015EJ0300 Rev.3.00 Page 613 of 870
Sep 30, 2010
18.2 Configuration
CPU
Internal RAM
On-chip
peripheral I/O
On-chip peripheral I/O bus
Internal bus
Data
control
Address
control
Count
control
Channel
control
DMAC
V850ES/JG3
Bus interface
External bus
External
RAM
External
ROM
External I/O
DMA source address
register n (DSAnH/DSAnL)
DMA transfer count
register n (DBCn)
DMA channel control
register n (DCHCn)
DMA destination address
register n (DDAnH/DDAnL)
DMA addressing control
register n (DADCn)
DMA trigger factor
register n (DTFRn)
Remark n = 0 to 3