Datasheet

V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER)
R01UH0015EJ0300 Rev.3.00 Page 612 of 870
Sep 30, 2010
CHAPTER 18 DMA FUNCTION (DMA CONTROLLER)
The V850ES/JG3 includes a direct memory access (DMA) controller (DMAC) that executes and controls DMA transfer.
The DMAC controls data transfer between memory and I/O, between memories, or between I/Os based on DMA
requests issued by the on-chip peripheral I/O (serial interface, timer/counter, and A/D converter), interrupts from external
input pins, or software triggers (memory refers to internal RAM or external memory).
18.1 Features
• 4 independent DMA channels
• Transfer unit: 8/16 bits
• Maximum transfer count: 65,536 (2
16
)
• Transfer type: Two-cycle transfer
• Transfer mode: Single transfer mode
• Transfer requests
• Request by interrupts from on-chip peripheral I/O (serial interface, timer/counter, A/D converter) or interrupts from
external input pin
• Requests by software trigger
• Transfer targets
• Internal RAM ↔ Peripheral I/O
• Peripheral I/O ↔ Peripheral I/O
• Internal RAM ↔ External memory
• External memory ↔ Peripheral I/O
• External memory ↔ External memory