Datasheet

V850ES/JG3 CHAPTER 17 I
2
C BUS
R01UH0015EJ0300 Rev.3.00 Page 611 of 870
Sep 30, 2010
Figure 17-24. Example of Slave to Master Communication
(When 8-Clock → 9-Clock Wait for Master and 9-Clock Wait for Slave Are Selected) (3/3)
(c) Stop condition
IICn
ACKDn
STDn
SPDn
WTIMn
H
H
L
L
L
ACKEn
MSTSn
STTn
SPTn
WRELn
INTIICn
TRCn
IICn
ACKDn
STDn
SPDn
WTIMn
ACKEn
MSTSn
STTn
SPTn
WRELn
INTIICn
TRCn
SCL0n
SDA0n
Processing by master device
Transfer lines
Processing by slave device
12345678 9 1
D7 D6 D5 D4 D3 D2 D1 D0 AD6
IICn ← address
IICn
← FFH Note
Note
IICn
← data
Stop
condition
Start
condition
(when SPIEn = 1)
NACK
(when SPIEn = 1)
Note To cancel master wait, write FFH to IICn or set WRELn.
Remark n = 0 to 2