Datasheet

V850ES/JG3 CHAPTER 17 I
2
C BUS
R01UH0015EJ0300 Rev.3.00 Page 609 of 870
Sep 30, 2010
Figure 17-24. Example of Slave to Master Communication
(When 8-Clock Wait for Master and 9-Clock Wait for Slave Are Selected) (1/3)
(a) Start condition ~ address
IICn
ACKDn
STDn
SPDn
WTIMn
H
H
L
L
L
H
L
ACKEn
MSTSn
STTn
L
L
SPTn
WRELn
INTIICn
TRCn
IICn
ACKDn
STDn
SPDn
WTIMn
ACKEn
MSTSn
STTn
SPTn
WRELn
INTIICn
TRCn
SCL0n
SDA0n
Processing by master device
Transfer lines
Processing by slave device
123456789 4 56321
AD6 AD5 AD4 AD3 AD2 AD1 AD0 R D4 D3 D2D5D6D7
IICn ← address IICn ← FFH Note
Note
IICn
← data
Start condition
ACK
Note To cancel master wait, write FFH to IICn or set WRELn.
Remark n = 0 to 2