Datasheet

V850ES/JG3 CHAPTER 17 I
2
C BUS
R01UH0015EJ0300 Rev.3.00 Page 606 of 870
Sep 30, 2010
Figure 17-23. Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Both Master and Slave) (1/3)
(a) Start condition ~ address
IICn
ACKDn
STDn
SPDn
WTIMn
H
H
L
L
L
L
H
H
H
L
L
ACKEn
MSTSn
STTn
SPTn
WRELn
INTIICn
TRCn
IICn
ACKDn
STDn
SPDn
WTIMn
ACKEn
MSTSn
STTn
SPTn
WRELn
INTIICn
TRCn
SCL0n
SDA0n
Processing by master device
Transfer lines
Processing by slave device
123456789 4321
AD6 AD5 AD4 AD3 AD2 AD1 AD0 W ACK D4D5D6D7
IICn
← address IICn ← data
IICn
← FFH
Transmit
Start condition
Receive
(when EXCn = 1)
Note
Note
Note To cancel slave wait, write FFH to IICn or set WRELn.
Remark n = 0 to 2