Datasheet

V850ES/JG3 CHAPTER 17 I
2
C BUS
R01UH0015EJ0300 Rev.3.00 Page 599 of 870
Sep 30, 2010
17.16.2 Master operation in multimaster system
Figure 17-19. Master Operation in Multimaster System (1/3)
IICXn ← 0XH
IICCLn ← XXH
OCKSm ← XXH
IICFn ← 0XH
Set STCENn, IICRSVn
IICCn ← XXH
ACKEn = WTIMn = SPIEn = 1
IICEn = 1
Set ports
SPTn = 1
SVAn ← XXH
SPIEn = 1
START
Slave operation
Slave operation
Bus release status for a certain period
Confirmation of bus
status is in progress
Yes
Confirm bus status
Note
Master operation
started?
Communication
reservation enable
Communication
reservation disable
SPDn = 1?
STCENn = 1?
IICRSVn = 0?
A
Refer to Table 4-15 Settings When Port Pins Are Used for Alternate Functions
to set the I
2
C mode before this function is used.
Transfer clock selection
Local address setting
Start condition setting
(communication start
request issued)
(no communication start request)
• Waiting for slave specification from another master
• Waiting for communication start request (depending on user program)
Communication start preparation
(stop condition generation)
Waiting for stop condition
detection
No
Yes
Yes
No
INTIICn interrupt
occurred?
INTIICn interrupt
occurred?
Yes
No
Yes
No
SPDn = 1?
Yes
No
Slave operation
No
INTIICn interrupt
occurred?
Yes
No
1
B
SPIEn = 0
Yes
No
Waiting for communication request
Communication waiting
Initial settings
Note Confirm that the bus release status (IICCLn.CLDn bit = 1, IICCLn.DADn bit = 1) has been maintained for a
certain period (1 frame, for example). When the SDA0n pin is constantly low level, determine whether to
release the I
2
C0n bus (SCL0n, SDA0n pins = high level) by referring to the specifications of the product in
communication.
Remark n = 0 to 2, m = 0, 1