Datasheet

V850ES/JG3 CHAPTER 17 I
2
C BUS
R01UH0015EJ0300 Rev.3.00 Page 598 of 870
Sep 30, 2010
17.16.1 Master operation in single master system
Figure 17-18. Master Operation in Single Master System
IICXn ← 0XH
IICCLn ← XXH
OCKSm ← XXH
IICFn ← 0XH
Set STCENn, IICRSVn = 0
IICCn ← XXH
ACKEn = WTIMn = SPIEn = 1
IICEn = 1
Set ports
Initialize I
2
C bus
Note
SPTn = 1
SVAn ← XXH
Write IICn
Write IICn
SPTn = 1
WRELn = 1
START
END
Read IICn
ACKEn = 0
WTIMn = WRELn = 1
No
No
Yes
No
No
No
Yes
Yes
Yes
Yes
STCENn = 1?
ACKEn = 1
WTIMn = 0
INTIICn
interrupt occurred?
Transfer completed?
Transfer completed?
Restarted?
TRCn = 1?
ACKDn = 1?
ACKDn = 1?
Refer to Table 4-15 Settings When Port Pins Are Used for Alternate Functions
to set the I
2
C mode before this function is used.
Transfer clock selection
Local address setting
Start condition setting
Communication start preparation
(start condition generation)
Communication start
(address, transfer direction specification)
Waiting for ACK detection
Waiting for data transmission
Transmission start
Communication processing
Initial settings
Reception start
Waiting for
data reception
No
Yes
INTIICn
interrupt occurred?
Waiting for ACK detection
Communication start preparation
(stop condition generation)
Waiting for stop condition detection
No
Yes
Yes
No
INTIICn
interrupt occurred?
Yes
No
INTIICn
interrupt occurred?
Yes
No
Yes
No
Yes
No
INTIICn
interrupt occurred?
STTn = 1
Note Release the I
2
C0n bus (SCL0n, SDA0n pins = high level) in conformity with the specifications of the product
in communication.
For example, when the EEPROM
TM
outputs a low level to the SDA0n pin, set the SCL0n pin to the output port
and output clock pulses from that output port until when the SDA0n pin is constantly high level.
Remarks 1. For the transmission and reception formats, conform to the specifications of the product in
communication.
2. n = 0 to 2, m = 0, 1