Datasheet

V850ES/JG3 CHAPTER 17 I
2
C BUS
R01UH0015EJ0300 Rev.3.00 Page 581 of 870
Sep 30, 2010
(4) When arbitration loss occurs due to restart condition during data transfer
<1> Not extension code (Example: Address mismatch)
ST AD6 to AD0 R/W ACK D7 to Dn ST AD6 to AD0 R/W ACK D7 to D0 ACK SP
S1 S2 Δ3
S1: IICSn register = 1000X110B
S2: IICSn register = 01000110B (Example: When ALDn bit is read during interrupt servicing)
Δ 3: IICSn register = 00000001B
Remarks 1. S: Always generated
Δ: Generated only when SPIEn bit = 1
X: don’t care
2. Dn = D6 to D0
n = 0 to 2
<2> Extension code
ST AD6 to AD0 R/W ACK D7 to Dn ST AD6 to AD0 R/W ACK D7 to D0 ACK SP
S1 S2 Δ3
S1: IICSn register = 1000X110B
S2: IICSn register = 0110X010B (Example: When ALDn bit is read during interrupt servicing)
IICCn.LRELn bit is set to 1 by software
Δ 3: IICSn register = 00000001B
Remarks 1. S: Always generated
Δ: Generated only when SPIEn bit = 1
X: don’t care
2. Dn = D6 to D0
n = 0 to 2