Datasheet

V850ES/JG3 CHAPTER 3 CPU FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 43 of 870
Sep 30, 2010
(3) On-chip peripheral I/O area
4 KB of addresses 03FFF000H to 03FFFFFFH are reserved as the on-chip peripheral I/O area.
Figure 3-11. On-Chip Peripheral I/O Area
On-chip peripheral I/O area
(4 KB)
03FFFFFFH
03FFF000H
FFFFFFFFH
FFFFF000H
Physical address space Logical address space
Peripheral I/O registers that have functions to specify the operation mode for and monitor the status of the on-chip
peripheral I/O are mapped to the on-chip peripheral I/O area. Program cannot be fetched from this area.
Cautions 1. When a register is accessed in word units, a word area is accessed twice in halfword units in
the order of lower area and higher area, with the lower 2 bits of the address ignored.
2. If a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits
are undefined when the register is read, and data is written to the lower 8 bits.
3. Addresses not defined as registers are reserved for future expansion. The operation is
undefined and not guaranteed when these addresses are accessed.
(4) External memory area
15 MB (00100000H to 00FFFFFFH) are allocated as the external memory area. For details, see CHAPTER 5
BUS CONTROL FUNCTION.