Datasheet

V850ES/JG3 CHAPTER 17 I
2
C BUS
R01UH0015EJ0300 Rev.3.00 Page 569 of 870
Sep 30, 2010
17.7.2 Slave device operation (when receiving slave address data (address match))
(1) Start ~ Address ~ Data ~ Data ~ Stop
<1> When IICCn.WTIMn bit = 0
ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK SP
S1 S2 S3 Δ4
S1: IICSn register = 0001X110B
S2: IICSn register = 0001X000B
S3: IICSn register = 0001X000B
Δ 4: IICSn register = 00000001B
Remarks 1. S: Always generated
Δ: Generated only when IICCn.SPIEn bit = 1
X: don’t care
2. n = 0 to 2
<2> When WTIMn bit = 1
ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK SP
S1 S2 S3 Δ4
S1: IICSn register = 0001X110B
S2: IICSn register = 0001X100B
S3: IICSn register = 0001XX00B
Δ 4: IICSn register = 00000001B
Remarks 1. S: Always generated
Δ: Generated only when SPIEn bit = 1
X: don’t care
2. n = 0 to 2