Datasheet

V850ES/JG3 CHAPTER 17 I
2
C BUS
R01UH0015EJ0300 Rev.3.00 Page 567 of 870
Sep 30, 2010
(2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart)
<1> When WTIMn bit = 0
STTn bit = 1 SPTn bit = 1
↓ ↓
ST AD6 to AD0 R/W ACK D7 to D0 ACK ST AD6 to AD0 R/W ACK D7 to D0 ACK SP
S1 S2 S3 S4 S5 S6 Δ7
S1: IICSn register = 1000X110B
S2: IICSn register = 1000X000B (WTIMn bit = 1)
S3: IICSn register = 1000XX00B (WTIMn bit = 0)
S4: IICSn register = 1000X110B (WTIMn bit = 0)
S5: IICSn register = 1000X000B (WTIMn bit = 1)
S6: IICSn register = 1000XX00B
Δ 7: IICSn register = 00000001B
Remarks 1. S: Always generated
Δ: Generated only when SPIEn bit = 1
X: don’t care
2. n = 0 to 2
<2> When WTIMn bit = 1
STTn bit = 1 SPTn bit = 1
↓ ↓
ST AD6 to AD0 R/W ACK D7 to D0 ACK ST AD6 to AD0 R/W ACK D7 to D0 ACK SP
S1 S2 S3 S4 Δ5
S1: IICSn register = 1000X110B
S2: IICSn register = 1000XX00B
S3: IICSn register = 1000X110B
S4: IICSn register = 1000XX00B
Δ 5: IICSn register = 00000001B
Remarks 1. S: Always generated
Δ: Generated only when SPIEn bit = 1
X: don’t care
2. n = 0 to 2