Datasheet

V850ES/JG3 CHAPTER 17 I
2
C BUS
R01UH0015EJ0300 Rev.3.00 Page 564 of 870
Sep 30, 2010
Figure 17-13. Wait State (2/2)
(b) When master and slave devices both have a nine-clock wait
(master: transmission, slave: reception, and ACKEn bit = 1)
SCL0n
6
SDA0n
789 123
SCL0n
IICn
6
H
78 1 23
D2 D1 D0 ACK D7 D6 D5
9
IICn
SCL0n
ACKEn
Master
Master and slave both wait
after output of ninth clock.
IICn data write (cancel wait state)
Slave
FFH is written to IICn register
or WRELn bit is set to 1.
Generated according to previously set ACKEn bit value
Transfer lines
Wait state
from master/
slave
Wait state
from slave
Remark n = 0 to 2
A wait state may be automatically generated depending on the setting of the IICCn.WTIMn bit (n = 0 to 2).
Normally, when the IICCn.WRELn bit is set to 1 or when FFH is written to the IICn register on the receiving side, the
wait state is canceled and the transmitting side writes data to the IICn register to cancel the wait state.
The master device can also cancel the wait state via either of the following methods.
• By setting the IICCn.STTn bit to 1
• By setting the IICCn.SPTn bit to 1