Datasheet

V850ES/JG3 CHAPTER 17 I
2
C BUS
R01UH0015EJ0300 Rev.3.00 Page 563 of 870
Sep 30, 2010
17.6.6 Wait state
A wait state is used to notify the communication partner that a device (master or slave) is preparing to transmit or
receive data (i.e., is in a wait state).
Setting the SCL0n pin to low level notifies the communication partner of the wait state. When the wait state has been
canceled for both the master and slave devices, the next data transfer can begin (n = 0 to 2).
Figure 17-13. Wait State (1/2)
(a) When master device has a nine-clock wait and slave device has an eight-clock wait
(master: transmission, slave: reception, and IICCn.ACKEn bit = 1)
SCL0n
6
SDA0n
78 9 123
SCL0n
IICn
6
H
78 123
D2 D1 D0 ACK D7 D6 D5
9
IICn
SCL0n
ACKEn
Master
Master returns to high
impedance but slave
is in wait state (low level).
Wait after output
of ninth clock.
IICn data write (cancel wait state)
Slave
Wait after output
of eighth clock.
FFH is written to IICn register or
IICCn.WRELn bit is set to 1.
Transfer lines
Wait state
from slave
Wait state
from master
Remark n = 0 to 2