Datasheet

V850ES/JG3 CHAPTER 17 I
2
C BUS
R01UH0015EJ0300 Rev.3.00 Page 559 of 870
Sep 30, 2010
17.6.2 Addresses
The 7 bits of data that follow the start condition are defined as an address.
An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the
master device via the bus lines. Therefore, each slave device connected via the bus lines must have a unique address.
The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data
matches the data values stored in the SVAn register. If the address data matches the values of the SVAn register, the
slave device is selected and communicates with the master device until the master device generates a start condition or
stop condition (n = 0 to 2).
Figure 17-9. Address
Address
SCL0n
1
SDA0n
INTIICn
Note
23456789
AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W
Note The interrupt request signal (INTIICn) is generated if a local address or extension code is received
during slave device operation.
Remark n = 0 to 2
The slave address and the eighth bit, which specifies the transfer direction as described in 17.6.3 Transfer direction
specification below, are written together to IIC shift register n (IICn) and then output. Received addresses are written to
the IICn register (n = 0 to 2).
The slave address is assigned to the higher 7 bits of the IICn register.