Datasheet

V850ES/JG3 CHAPTER 17 I
2
C BUS
R01UH0015EJ0300 Rev.3.00 Page 555 of 870
Sep 30, 2010
(7) IIC division clock select registers 0, 1 (OCKS0, OCKS1)
The OCKSm register controls the I
2
C0n division clock (n = 0 to 2, m = 0, 1).
This register controls the I
2
C00 division clock via the OCKS0 register and the I
2
C01 and I
2
C02 division clocks via
the OCKS1 register.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
0OCKSm
(m = 0, 1)
00 OCKSENm OCKSTHm 0 OCKSm1 OCKSm0
After reset: 00H R/W Address: OCKS0 FFFFF340H, OCKS1 FFFFF344H
Disable I
2
C division clock operation
Enable I
2
C division clock operation
OCKSENm
0
1
Operation setting of I
2
C division clock
OCKSm1
0
0
1
1
0
Other than above
OCKSm0
0
1
0
1
0
Selection of I
2
C division clock
f
XX /2
f
XX /3
f
XX /4
f
XX /5
f
XX
Setting prohibited
OCKSTHm
0
0
0
0
1
(8) IIC shift registers 0 to 2 (IIC0 to IIC2)
The IICn register is used for serial transmission/reception (shift operations) synchronized with the serial clock.
This register can be read or written in 8-bit units, but data should not be written to the IICn register during a data
transfer.
Access (read/write) the IICn register only during the wait period. Accessing this register in communication states
other than the wait period is prohibited. However, for the master device, the IICn register can be written once only
after the transmission trigger bit (IICCn.STTn bit) has been set to 1.
A wait state is released by writing the IICn register during the wait period, and data transfer is started (n = 0 to 2).
Reset sets this register to 00H.
After reset: 00H R/W Address: IIC0 FFFFFD80H, IIC1 FFFFFD90H, IIC2 FFFFFDA0H
7 6 5 4 3 2 1 0
IICn
(n = 0 to 2)