Datasheet

V850ES/JG3 CHAPTER 17 I
2
C BUS
R01UH0015EJ0300 Rev.3.00 Page 553 of 870
Sep 30, 2010
Table 17-2. Clock Settings (1/2)
IICX0 IICCL0
Bit 0 Bit 3 Bit 1 Bit 0
CLX0 SMC0 CL01 CL00
Selection Clock Transfer
Clock
Settable Main Clock
Frequency (f
XX) Range
Operating
Mode
fXX (when OCKS0 = 18H set) fXX/44 2.00 MHz ≤ fXX ≤ 4.19 MHz
fXX/2 (when OCKS0 = 10H set) fXX/88 4.00 MHz ≤ fXX ≤ 8.38 MHz
fXX/3 (when OCKS0 = 11H set) fXX/132 6.00 MHz ≤ fXX ≤ 12.57 MHz
fXX/4 (when OCKS0 = 12H set) fXX/176 8.00 MHz ≤ fXX ≤ 16.76 MHz
0 0 0 0
f
XX/5 (when OCKS0 = 13H set) fXX/220 10.00 MHz ≤ fXX ≤ 20.95 MHz
fXX (when OCKS0 = 18H set) fXX/86 4.19 MHz ≤ fXX ≤ 8.38 MHz
fXX/2 (when OCKS0 = 10H set) fXX/172 8.38 MHz ≤ fXX ≤ 16.76 MHz
fXX/3 (when OCKS0 = 11H set) fXX/258 12.57 MHz ≤ fXX ≤ 25.14 MHz
fXX/4 (when OCKS0 = 12H set) fXX/344 16.76 MHz ≤ fXX ≤ 32.00 MHz
0 0 0 1
f
XX/5 (when OCKS0 = 13H set) fXX/430 20.95 MHz ≤ fXX ≤ 32.00 MHz
0 0 1 0
f
XX
Note
fXX/86 4.19 MHz ≤ fXX ≤ 8.38 MHz
fXX (when OCKS0 = 18H set) fXX/66 6.40 MHz
fXX/2 (when OCKS0 = 10H set) fXX/132 12.80 MHz
fXX/3 (when OCKS0 = 11H set) fXX/198 19.20 MHz
fXX/4 (when OCKS0 = 12H set) fXX/264 25.60 MHz
0 0 1 1
f
XX/5 (when OCKS0 = 13H set) fXX/330 32.00 MHz
Standard mode
(SMC0 bit = 0)
fXX (when OCKS0 = 18H set) fXX/24 4.19 MHz ≤ fXX ≤ 8.38 MHz
fXX/2 (when OCKS0 = 10H set) fXX/48 8.00 MHz ≤ fXX ≤ 16.76 MHz
fXX/3 (when OCKS0 = 11H set) fXX/72 12.00 MHz ≤ fXX ≤ 25.14 MHz
0 1 0
×
f
XX/4 (when OCKS0 = 12H set) fXX/96 16.00 MHz ≤ fXX ≤ 32.00 MHz
0 1 1 0
f
XX
Note
fXX/24 4.00 MHz ≤ fXX ≤ 8.38 MHz
fXX (when OCKS0 = 18H set) fXX/18 6.40 MHz
fXX/2 (when OCKS0 = 10H set) fXX/36 12.80 MHz
fXX/3 (when OCKS0 = 11H set) fXX/54 19.20 MHz
fXX/4 (when OCKS0 = 12H set) fXX/72 25.60 MHz
0 1 1 1
f
XX/5 (when OCKS0 = 13H set) fXX/90 32.00 MHz
fXX (when OCKS0 = 18H set) fXX/12 4.00 MHz ≤ fXX ≤ 4.19 MHz
fXX/2 (when OCKS0 = 10H set) fXX/24 8.00 MHz ≤ fXX ≤ 8.38 MHz
fXX/3 (when OCKS0 = 11H set) fXX/36 12.00 MHz ≤ fXX ≤ 12.57 MHz
fXX/4 (when OCKS0 = 12H set) fXX/48 16.00 MHz ≤ fXX ≤ 16.67 MHz
1 1 0
×
f
XX/5 (when OCKS0 = 13H set) fXX/60 20.00 MHz ≤ fXX ≤ 20.95 MHz
1 1 1 0
f
XX
Note
fXX/12 4.00 MHz ≤ fXX ≤ 4.19 MHz
High-speed
mode
(SMC0 bit = 1)
Other than above Setting prohibited
− − −
Note Since the selection clock is f
XX regardless of the value set to the OCKS0 register, clear the OCKS0 register to
00H (I
2
C division clock stopped status).
Remark ×: don’t care