Datasheet
V850ES/JG3 CHAPTER 17 I
2
C BUS
R01UH0015EJ0300 Rev.3.00 Page 547 of 870
Sep 30, 2010
(2/3)
COIn Matching address detection
0 Addresses do not match.
1 Addresses match.
Condition for clearing (COIn bit = 0) Condition for setting (COIn bit = 1)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LRELn bit = 1 (communication save)
• When the IICEn bit changes from 1 to 0 (operation
stop)
• After reset
• When the received address matches the local
address (SVAn register) (set at the rising edge of the
eighth clock).
TRCn Transmit/receive status detection
0 Receive status (other than transmit status). The SDA0n line is set to high impedance.
1 Transmit status. The value in the SO latch is enabled for output to the SDA0n line (valid starting at
the falling edge of the first byte’s ninth clock).
Condition for clearing (TRCn bit = 0) Condition for setting (TRCn bit = 1)
• When a stop condition is detected
• Cleared by LRELn bit = 1 (communication save)
• When the IICEn bit changes from 1 to 0 (operation
stop)
• Cleared by IICCn.WRELn bit = 1
Note
• When the ALDn bit changes from 0 to 1 (arbitration
loss)
• After reset
Master
• When “1” is output to the first byte’s LSB (transfer
direction specification bit)
Slave
• When a start condition is detected
When not used for communication
Master
• When a start condition is generated
• When “0” is output to the first byte’s LSB (transfer
direction specification bit)
Slave
• When “1” is input by the first byte’s LSB (transfer
direction specification bit)
ACKDn ACK detection
0 ACK was not detected.
1 ACK was detected.
Condition for clearing (ACKDn bit = 0) Condition for setting (ACKDn bit = 1)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
• Cleared by LRELn bit = 1 (communication save)
• When the IICEn bit changes from 1 to 0 (operation
stop)
• After reset
• After the SDA0n bit is set to low level at the rising
edge of the SCL0n pin’s ninth clock
Note The TRCn bit is cleared to 0 and SDA0n line becomes high impedance when the WRELn bit is set to
1 and the wait state is canceled to 0 at the ninth clock by TRCn bit = 1.
Remark n = 0 to 2