Datasheet

V850ES/JG3 CHAPTER 17 I
2
C BUS
R01UH0015EJ0300 Rev.3.00 Page 545 of 870
Sep 30, 2010
(4/4)
SPTn Stop condition trigger
0
Stop condition is not generated.
1 Stop condition is generated (termination of master device’s transfer).
After the SDA0n line goes to low level, either set the SCL0n line to high level or wait until the SCL0n
pin goes to high level. Next, after the rated amount of time has elapsed, the SDA0n line is changed
from low level to high level and a stop condition is generated.
Cautions concerning set timing
For master reception: Cannot be set to 1 during transfer.
Can be set to 1 only when the ACKEn bit has been set to 0 and during the wait period
after the slave has been notified of final reception.
For master transmission: A stop condition cannot be generated normally during the ACK reception period. Set to
1 during the wait period that follows output of the ninth clock.
• Cannot be set to 1 at the same time as the STTn bit.
• The SPTn bit can be set to 1 only when in master mode
Note
.
• When the WTIMn bit has been set to 0, if the SPTn bit is set to 1 during the wait period that follows output of
eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock.
The WTIMn bit should be changed from 0 to 1 during the wait period following output of eight clocks, and the
SPTn bit should be set to 1 during the wait period that follows output of the ninth clock.
• When the SPTn bit is set to 1, setting the SPTn bit to 1 again is disabled until the setting is cleared to 0.
Condition for clearing (SPTn bit = 0) Condition for setting (SPTn bit = 1)
• Cleared by loss in arbitration
• Automatically cleared after stop condition is detected
• When the LRELn bit = 1 (communication save)
• When the IICEn bit = 0 (operation stop)
• After reset
• Set by instruction
Note Set the SPTn bit to 1 only in master mode. However, when the IICRSVn bit is 0, the SPTn bit must be set
to 1 and a stop condition generated before the first stop condition is detected following the switch to the
operation enabled status. For details, see 17.15 Cautions.
Caution When the TRCn bit = 1, the WRELn bit is set to 1 during the ninth clock and the wait state
is canceled, after which the TRCn bit is cleared to 0 and the SDA0n line is set to high
impedance.
Remarks 1. The SPTn bit is 0 if it is read immediately after data setting.
2. n = 0 to 2