Datasheet

V850ES/JG3 CHAPTER 17 I
2
C BUS
R01UH0015EJ0300 Rev.3.00 Page 541 of 870
Sep 30, 2010
17.4 Registers
I
2
C00 to I
2
C02 are controlled by the following registers.
• IIC control registers 0 to 2 (IICC0 to IICC2)
• IIC status registers 0 to 2 (IICS0 to IICS2)
• IIC flag registers 0 to 2 (IICF0 to IICF2)
• IIC clock select registers 0 to 2 (IICCL0 to IICCL2)
• IIC function expansion registers 0 to 2 (IICX0 to IICX2)
• IIC division clock select registers 0, 1 (OCKS0, OCKS1)
The following registers are also used.
• IIC shift registers 0 to 2 (IIC0 to IIC2)
• Slave address registers 0 to 2 (SVA0 to SVA2)
Remark For the alternate-function pin settings, see Table 4-15 Using Port Pin as Alternate-Function Pin.
(1) IIC control registers 0 to 2 (IICC0 to IICC2)
The IICCn register enables/stops I
2
C0n operations, sets the wait timing, and sets other I
2
C operations (n = 0 to 2).
This register can be read or written in 8-bit or 1-bit units. However, set the SPIEn, WTIMn, and ACKEn bits when
the IICEn bit is 0 or during the wait period. When setting the IICEn bit from “0” to “1”, these bits can also be set at
the same time.
Reset sets this register to 00H.