Datasheet

V850ES/JG3 CHAPTER 17 I
2
C BUS
R01UH0015EJ0300 Rev.3.00 Page 537 of 870
Sep 30, 2010
17.3 Configuration
The block diagram of the I
2
C0n is shown below.
Figure 17-4. Block Diagram of I
2
C0n
Internal bus
IIC status register n (IICSn)
IIC control register n
(IICCn)
SO latch
IICEn
DQ
CLn1,
CLn0
TRCn
DFCn
DFCn
SDA0n
SCL0n
Output control
INTIICn
IIC shift register n
(IICn)
IICCn.STTn, SPTn
IICSn.MSTSn, EXCn, COIn
IICSn.MSTSn,
EXCn, COIn
LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn
MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn
Internal bus
CLDn DADn SMCn DFCn CLn1 CLn0 CLXn
IIC clock select
register n (IICCLn)
STCFn IICBSYn STCENn IICRSVn
IIC flag register n
(IICFn)
IIC function expansion
register n (IICXn)
fxx
IIC division clock select
register m (OCKSm)
fxx to fxx/5
OCKSTHmOCKSENm OCKSm1 OCKSm0
Clear
Slave address
register n (SVAn)
Match
signal
Set
Noise
eliminator
IIC shift
register n (IICn)
Data
retention time
correction
circuit
N-ch open-drain
output
ACK detector
ACK
generator
Start condition
detector
Stop condition
detector
Serial clock counter
Serial clock
controller
Noise
eliminator
N-ch open-drain
output
Start
condition
generator
Stop
condition
generator
Wakeup controller
Interrupt request
signal generator
Serial clock
wait controller
Bus status
detector
Prescaler
Prescaler
Remark n = 0 to 2
m = 0, 1