Datasheet

V850ES/JG3 CHAPTER 17 I
2
C BUS
R01UH0015EJ0300 Rev.3.00 Page 536 of 870
Sep 30, 2010
17.2 Features
I
2
C00 to I
2
C02 have the following two modes.
• Operation stopped mode
• I
2
C (Inter IC) bus mode (multimasters supported)
(1) Operation stopped mode
In this mode, serial transfers are not performed, thus enabling a reduction in power consumption.
(2) I
2
C bus mode (multimaster support)
This mode is used for 8-bit data transfers with several devices via two lines: a serial clock pin (SCL0n) and a serial
data bus pin (SDA0n).
This mode complies with the I
2
C bus format and the master device can generate “start condition”, “address”,
“transfer direction specification”, “data”, and “stop condition” data to the slave device via the serial data bus. The
slave device automatically detects the received statuses and data by hardware. This function can simplify the part
of an application program that controls the I
2
C bus.
Since SCL0n and SDA0n pins are used for N-ch open-drain outputs, I
2
C0n requires pull-up resistors for the serial
clock line and the serial data bus line.
Remark n = 0 to 2