Datasheet

V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
R01UH0015EJ0300 Rev.3.00 Page 530 of 870
Sep 30, 2010
16.8 Baud Rate Generator
The BRG1 to BRG3 and CSIB0 to CSIB4 baud rate generators are connected as shown in the following block diagram.
CSIB0
CSIB1
CSIB2
CSIB3
CSIB4
BRG1
BRG2
BRG3
f X
f X
f X
f BRG1
f BRG2
f BRG3
(1) Prescaler mode registers 1 to 3 (PRSM1 to PRSM3)
The PRSM1 to PRSM3 registers control generation of the baud rate signal for CSIB.
These registers can be read or written in 8-bit or 1-bit units.
Reset sets these registers to 00H.
0PRSMm
(m = 1 to 3)
0 0 BGCEm 0 0 BGCSm1 BGCSm0
Disabled
Enabled
BGCEm
0
1
Baud rate output
f XX
f XX /2
f XX /4
f XX /8
Setting value (k)
0
1
2
3
BGCSm1
0
0
1
1
BGCSm0
0
1
0
1
Input clock selection (f
BGCSm )
After reset: 00H R/W Address: PRSM1 FFFFF320H, PRSM2 FFFFF324H,
PRSM3 FFFFF328H
< >
Cautions 1. Do not rewrite the PRSMm register during operation.
2. Set the PRSMm register before setting the BGCEm bit to 1.
3. Be sure to clear bits 7 to 5, 3, and 2 to “0”.