Datasheet

V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
R01UH0015EJ0300 Rev.3.00 Page 529 of 870
Sep 30, 2010
16.7 Output Pins
(1) SCKBn pin
When CSIBn operation is disabled (CBnCTL0.CBnPWR bit = 0), the SCKBn pin output status is as follows.
CBnCKP CBnCKS2 CBnCKS1 CBnCKS0 SCKBn Pin Output
1 1 1 High impedance 0
Other than above Fixed to high level
1 1 1 High impedance 1
Other than above Fixed to low level
Remarks 1. The output level of the SCKBn pin changes if any of the CBnCTL1.CBnCKP and CBnCKS2 to
CBnCKS0 bits is rewritten.
2. n = 0 to 4
(2) SOBn pin
When CSIBn operation is disabled (CBnPWR bit = 0), the SOBn pin output status is as follows.
CBnTXE CBnDAP CBnDIR SOBn Pin Output
0
× ×
Fixed to low level
0
×
SOBn latch value (low level)
0 CBnTX0 value (MSB)
1
1
1 CBnTX0 value (LSB)
Remarks 1. The SOBn pin output changes when any one of the
CBnCTL0.CBnTXE, CBnCTL0.CBnDIR bits, and CBnCTL1.CBnDAP
bit is rewritten.
2. ×: Don’t care
3. n = 0 to 4