Datasheet

V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
R01UH0015EJ0300 Rev.3.00 Page 528 of 870
Sep 30, 2010
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(iii) Communication type 2 (CBnCKP and CBnDAP bits = 01)
D6 D5 D4 D3 D2 D1 D0D7
SCKBn pin
SIBn capture
Reg-R/W
SOBn pin
INTCBnT
interrupt
Note 1
INTCBnR
interrupt
Note 2
CBnTSF bit
(iv) Communication type 4 (CBnCKP and CBnDAP bits = 11)
D6 D5 D4 D3 D2 D1 D0D7
SCKBn pin
SIBn capture
Reg-R/W
SOBn pin
INTCBnT
interrupt
Note 1
INTCBnR
interrupt
Note 2
CBnTSF bit
Notes 1. The INTCBnT interrupt is set when the data written to the CBnTX register is transferred to the data shift
register in the continuous transmission or continuous transmission/reception modes. In the single
transmission or single transmission/reception modes, the INTCBnT interrupt request signal is not
generated, but the INTCBnR interrupt request signal is generated upon end of communication.
2. The INTCBnR interrupt occurs if reception is correctly ended and receive data is ready in the CBnRX
register while reception is enabled. In the single mode, the INTCBnR interrupt request signal is
generated even in the transmission mode, upon end of communication.
Caution In single transfer mode, writing to the CBnTX register with the CBnTSF bit set to 1 is ignored.
This has no influence on the operation during transfer.
For example, if the next data is written to the CBnTX register when DMA is started by generating
the INTCBnR signal, the written data is not transferred because the CBnTSF bit is set to 1.
Use the continuous transfer mode, not the single transfer mode, for such applications.