Datasheet

V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
R01UH0015EJ0300 Rev.3.00 Page 521 of 870
Sep 30, 2010
(2) Operation timing
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SCKBn pin
CBnTSF bit
(1)
(2)
(4)
(3) (5) (6) (7) (8) (9) (11) (13)(10)
SIBn pin
INTCBnR signal
CBnSCE bit
SIBn pin capture
timing
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
(1) Write 07H to the CBnCTL1 register, and select communication type 1, communication clock (fCCLK) =
external clock (SCKBn), and slave mode.
(2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits.
(3) Write A3H to the CBnCTL0 register, and select the reception mode, MSB first, and continuous transfer
mode at the same time as enabling the operation of the communication clock (f
CCLK).
(4) The CBnSTR.CBnTSF bit is set to 1 by performing a dummy read of the CBnRX register, and the
device waits for a serial clock input.
(5) When a serial clock is input, capture the receive data of the SIBn pin in synchronization with the serial
clock.
(6) When reception is completed, the reception completion interrupt request signal (INTCBnR) is
generated, and reading of the CBnRX register is enabled.
(7) When a serial clock is input in the CBnCTL0.CBnSCE bit = 1 status, continuous reception is started.
(8) To end continuous reception with the current reception, write the CBnSCE bit = 0.
(9) Read the CBnRX register.
(10) When reception is completed, the INTCBnR signal is generated, and reading of the CBnRX register is
enabled. When the CBnSCE bit = 0 is set before communication completion, clear the CBnTSF bit to
0 to end the receive operation.
(11) Read the CBnRX register.
(12) If an overrun error occurs, write the CBnSTR.CBnOVE bit = 0, and clear the error flag.
(13) To release the reception enable status, write the CBnCTL0.CBnPWR bit = 0 and the
CBnCTL0.CBnRXE bit = 0 after checking that the CBnTSF bit = 0.
Remark n = 0 to 4