Datasheet

V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
R01UH0015EJ0300 Rev.3.00 Page 515 of 870
Sep 30, 2010
(2) Operation timing
(1/2)
SCKBn pin
CBnTSF bit
(1)
(2)
(3)
(4) (5)
(6) (7) (8) (9) (10) (11) (13) (15)(12)
SIBn pin
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SOBn pin
INTCBnT signal
INTCBnR signal
SIBn pin capture
timing
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
(1) Write 00H to the CBnCTL1 register, and select communication type 1, communication clock (fCCLK) =
f
XX/2, and master mode.
(2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits.
(3) Write E3H to the CBnCTL0 register, and select the transmission/reception mode, MSB first, and
continuous transfer mode at the same time as enabling the operation of the communication clock
(f
CCLK).
(4) The CBnSTR.CBnTSF bit is set to 1 by writing the transmit data to the CBnTX register, and
transmission/reception is started.
(5) When transmission/reception is started, output the serial clock to the SCKBn pin, output the transmit
data to the SOBn pin in synchronization with the serial clock, and capture the receive data of the SIBn
pin.
(6) When transfer of the transmit data from the CBnTX register to the shift register is completed and
writing to the CBnTX register is enabled, the transmission enable interrupt request signal (INTCBnT) is
generated.
(7) To continue transmission/reception, write the transmit data to the CBnTX register again after the
INTCBnT signal is generated.
(8) When one transmission/reception is completed, the reception completion interrupt request signal
(INTCBnR) is generated, and reading of the CBnRX register is enabled.
(9) When a new transmit data is written to the CBnTX register before communication completion, the next
communication is started following communication completion.
(10) Read the CBnRX register.
Remark n = 0 to 4