Datasheet

V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
R01UH0015EJ0300 Rev.3.00 Page 514 of 870
Sep 30, 2010
(1) Operation flow
START
END
Yes
No
Is receive data
last data?
Yes (12)
No
Write CBnTX register
CBnOVE bit = 0
(CBnSTR)
Read CBnRX register
Read CBnRX register
CBnCTL1 register ← 00H
CBnCTL2 register ← 00H
CBnCTL0 register ← E3H
No (9)
Yes
(1), (2), (3)
(4)
(5)
(7)
(11)
(7)
(6), (11)
(8)
(13)
(13)
(14)
(15)
(15)
(10)
No
Yes
INTCBnT interrupt
generated?
No
Yes
CBnTSF bit = 0?
(CBnSTR)
Write CBnTX register
Yes
No
Is data being transmitted
last data?
Start transmission/reception
CBnCTL0 register ← 00H
CBnOVE bit = 1?
(CBnSTR)
INTCBnR interrupt
generated?
Remarks 1. The broken lines indicate the hardware processing.
2. The numbers in this figure correspond to the processing numbers in (2) Operation timing.
3. n = 0 to 4