Datasheet

V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
R01UH0015EJ0300 Rev.3.00 Page 511 of 870
Sep 30, 2010
(1) Operation flow
START
No
INTCBnR interrupt
generated?
CBnOVE bit = 1?
(CBnSTR)
END
Yes
No
Yes
CBnRX register
dummy read
CBnSCE bit = 0
(CBnCTL0)
CBnOVE bit = 0
(CBnSTR)
Read CBnRX register
Is data being received
last data?
Yes
CBnSCE bit = 0
(CBnCTL0)
Read CBnRX register
CBnCTL1 register ← 00H
CBnCTL2 register ← 00H
CBnCTL0 register ← A3H
Start reception
(1), (2), (3)
(4)
(5)
(6)
(8)
(9)
(12)
(13)
(13)
No
Read CBnRX register
(9)
(7)
Read CBnRX register
No
Yes
CBnCTL0 register ← 00H
No
Yes
CBnTSF bit = 0?
(CBnSTR)
(9)
(10)
(11)
(8)
INTCBnR interrupt
generated?
Remarks 1. The broken lines indicate the hardware processing.
2. The numbers in this figure correspond to the processing numbers in (2) Operation timing.
3. n = 0 to 4