Datasheet

V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
R01UH0015EJ0300 Rev.3.00 Page 500 of 870
Sep 30, 2010
16.6.3 Single transfer mode (master mode, transmission/reception mode)
MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00),
communication clock (fCCLK) = fXX/2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length = 8 bits
(CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000)
(1) Operation flow
START
(1), (2), (3)
(4)
(7), (9)
(5)
(6)
(10)
No (8)
Transmission/reception
completed?
END
Yes
CBnCTL1 register ← 07H
CBnCTL2 register ← 00H
CBnCTL0 register ← E1H
Write CBnTX register
Read CBnRX register
Start transmission/reception
CBnCTL0 ← 00H
No
INTCBnR interrupt
generated?
Yes
Yes
Remarks 1. The broken lines indicate the hardware processing.
2. The numbers in this figure correspond to the processing numbers in (2) Operation timing.
3. n = 0 to 4