Datasheet

V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
R01UH0015EJ0300 Rev.3.00 Page 498 of 870
Sep 30, 2010
16.6.2 Single transfer mode (master mode, reception mode)
MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00),
communication clock (fCCLK) = fXX/2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length = 8 bits
(CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000)
(1) Operation flow
START
No
INTCBnR interrupt
generated?
Reception completed?
END
Yes
Yes
No (7)
CBnRX register
dummy read
CBnSCE bit = 0
(CBnCTL0)
CBnCTL0 register ← 00H
Read CBnRX register
Read CBnRX register
CBnCTL1 register ← 00H
CBnCTL2 register ← 00H
CBnCTL0 register ← A1H
Start reception
(1), (2), (3)
(4)
(5)
(6)
(8)
(9)
(10)
Remarks 1. The broken lines indicate the hardware processing.
2. The numbers in this figure correspond to the processing numbers in (2) Operation timing.
3. n = 0 to 4