Datasheet

V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
R01UH0015EJ0300 Rev.3.00 Page 491 of 870
Sep 30, 2010
(2) CSIBn control register 1 (CBnCTL1)
CBnCTL1 is an 8-bit register that controls the CSIBn serial transfer operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Caution The CBnCTL1 register can be rewritten only when the CBnCTL0.CBnPWR bit = 0.
0
CBnCKP
0
0
1
1
Specification of data transmission/
reception timing in relation to SCKBn
CBnCTL1
(n = 0 to 4)
0
CBnDAP
0
1
0
1
0 CBnCKP CBnDAP
CBnCKS2 CBnCKS1 CBnCKS0
After reset 00H R/W Address: CB0CTL1 FFFFFD01H, CB1CTL1 FFFFFD11H,
CB2CTL1 FFFFFD21H, CB3CTL1 FFFFFD31H,
CB4CTL1 FFFFFD41H
CBnCKS2
0
0
0
0
1
1
1
1
CBnCKS1
0
0
1
1
0
0
1
1
CBnCKS0
0
1
0
1
0
1
0
1
Communication clock (f CCLK )
Note
f XX /2
f
XX /4
f
XX /8
f
XX /16
f
XX /32
f
XX /64
f
BRGm
External clock (SCKBn)
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Slave mode
Mode
D7 D6 D5 D4 D3 D2 D1 D0
SCKBn (I/O)
SIBn capture
SOBn (output)
D7 D6 D5 D4 D3 D2 D1 D0
SCKBn (I/O)
SIBn capture
SOBn (output)
D7 D6 D5 D4 D3 D2 D1 D0
SCKBn (I/O)
SIBn capture
SOBn (output)
D7 D6 D5 D4 D3 D2 D1 D0
SCKBn (I/O)
SIBn capture
SOBn (output)
Communication
type 1
Communication
type 2
Communication
type 3
Communication
type 4
Note Set the communication clock (f
CCLK) to 8 MHz or lower.
Remark When n = 0 or 1, m = 1
When n = 2 or 3, m = 2
When n = 4, m = 3
For details of f
BRGm, see 16.8 Baud Rate Generator.