Datasheet

V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
R01UH0015EJ0300 Rev.3.00 Page 486 of 870
Sep 30, 2010
16.3 Configuration
The following shows the block diagram of CSIBn.
Figure 16-3. Block Diagram of CSIBn
Internal bus
CBnCTL2CBnCTL0
CBnSTR
Controller
INTCBnR
f CCLK
SOBn
INTCBnT
CBnTX
SO latch
Phase
control
Shift register
CBnRX
CBnCTL1
Phase control
SIBn
f BRGm
f XX /2
f
XX /4
f
XX /8
f
XX /16
f
XX /32
f
XX /64
SCKBn
Selector
Remarks f
CCLK: Communication clock n = 0 to 4
f
XX: Main clock frequency m = 1 (n = 0, 1)
f
BRGm: BRGm count clock m = 2 (n = 2, 3)
m = 3 (n = 4)
CSIBn includes the following hardware.
Table 16-1. Configuration of CSIBn
Item Configuration
Registers
CSIBn receive data register (CBnRX)
CSIBn transmit data register (CBnTX)
Control registers
CSIBn control register 0 (CBnCTL0)
CSIBn control register 1 (CBnCTL1)
CSIBn control register 2 (CBnCTL2)
CSIBn status register (CBnSTR)