Datasheet

V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
R01UH0015EJ0300 Rev.3.00 Page 483 of 870
Sep 30, 2010
15.8 Cautions
(1) When the clock supply to UARTAn is stopped (for example, in IDLE1, IDLE2, or STOP mode), the operation stops
with each register retaining the value it had immediately before the clock supply was stopped. The TXDAn pin
output also holds and outputs the value it had immediately before the clock supply was stopped. However, the
operation is not guaranteed after the clock supply is resumed. Therefore, after the clock supply is resumed, the
circuits should be initialized by setting the UAnCTL0.UAnPWR, UAnCTL0.UAnRXEn, and UAnCTL0.UAnTXEn bits
to 000.
(2) The RXDA1 and KR7 pins must not be used at the same time. To use the RXDA1 pin, do not use the KR7 pin. To
use the KR7 pin, do not use the RXDA1 pin (it is recommended to set the PFC91 bit to 1 and clear PFCE91 bit to
0).
(3) In UARTAn, the interrupt caused by a communication error does not occur. When performing the transfer of
transmit data and receive data using DMA transfer, error processing cannot be performed even if errors (parity,
overrun, framing) occur during transfer. Either read the UAnSTR register after DMA transfer has been completed
to make sure that there are no errors, or read the UAnSTR register during communication to check for errors.
(4) Start up the UARTAn in the following sequence.
<1> Set the UAnCTL0.UAnPWR bit to 1.
<2> Set the ports.
<3> Set the UAnCTL0.UAnTXE bit to 1, UAnCTL0.UAnRXE bit to 1.
(5) Stop the UARTAn in the following sequence.
<1> Set the UAnCTL0.UAnTXE bit to 0, UAnCTL0.UAnRXE bit to 0.
<2> Set the ports and set the UAnCTL0.UAnPWR bit to 0 (it is not a problem if port setting is not changed).
(6) In transmit mode (UAnCTL0.UAnPWR bit = 1 and UAnCTL0.UAnTXE bit = 1), do not overwrite the same value to
the UAnTX register by software because transmission starts by writing to this register. To transmit the same value
continuously, overwrite the same value.
(7) In continuous transmission, the communication rate from the stop bit to the next start bit is extended 2 base clocks
more than usual. However, the reception side initializes the timing by detecting the start bit, so the reception result
is not affected.