Datasheet

V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
R01UH0015EJ0300 Rev.3.00 Page 480 of 870
Sep 30, 2010
(5) Allowable baud rate range during reception
The baud rate error range at the destination that is allowable during reception is shown below.
Caution The baud rate error during reception must be set within the allowable error range using the
following equation.
Figure 15-17. Allowable Baud Rate Range During Reception
FL
1 data frame (11 × FL)
FLmin
FLmax
UARTAn
transfer rate
Start bit
Bit 0 Bit 1 Bit 7
Parity bit
Minimum
allowable
transfer rate
Maximum
allowable
transfer rate
Stop bit
Start bit
Bit 0 Bit 1 Bit 7
Parity bit
Latch timing
Stop bit
Start bit
Bit 0 Bit 1 Bit 7
Parity bit
Stop bit
Remark n = 0 to 2
As shown in Figure 15-17, the receive data latch timing is determined by the counter set using the UAnCTL2
register following start bit detection. The transmit data can be normally received if up to the last data (stop bit) can
be received in time for this latch timing.
When this is applied to 11-bit reception, the following is the theoretical result.
FL = (Brate)
−
1
Brate: UARTAn baud rate (n = 0 to 2)
k: Setting value of UAnCTL2.UAnBRS7 to UAnCTL2.UAnBRS0 bits (n = 0 to 2)
FL: 1-bit data length
Latch timing margin: 2 clocks
Minimum allowable transfer rate: FLmin = 11 × FL − × FL = FL
k − 2
2k
21k + 2
2k