Datasheet

V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
R01UH0015EJ0300 Rev.3.00 Page 477 of 870
Sep 30, 2010
(3) UARTAn control register 2 (UAnCTL2)
The UAnCTL2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of UARTAn.
This register can be read or written in 8-bit units.
Reset sets this register to FFH.
Caution Clear the UAnCTL0.UAnPWR bit to 0 or clear the UAnTXE and UAnRXE bits to 00 before rewriting
the UAnCTL2 register.
UAnBRS7UAnCTL2
(n = 0 to 2)
UAnBRS6 UAnBRS5UAnBRS4 UAnBRS3UAnBRS2 UAnBRS1 UAnBRS0
654321
After reset FFH R/W Address: UA0CTL2 FFFFFA02H, UA1CTL2 FFFFFA12H,
UA2CTL2 FFFFFA22H
7 0
UAn
BRS7
0
0
0
0
:
1
1
1
1
UAn
BRS6
0
0
0
0
:
1
1
1
1
UAn
BRS5
0
0
0
0
:
1
1
1
1
UAn
BRS4
0
0
0
0
:
1
1
1
1
UAn
BRS3
0
0
0
0
:
1
1
1
1
UAn
BRS2
0
1
1
1
:
1
1
1
1
UAn
BRS1
×
0
0
1
:
0
0
1
1
UAn
BRS0
×
0
1
0
:
0
1
0
1
Default
(k)
×
4
5
6
:
252
253
254
255
Serial
clock
f
UCLK /4
f
UCLK /5
f
UCLK /6
:
f
UCLK /252
f
UCLK /253
f
UCLK /254
f
UCLK /255
Setting
prohibited
Remark f
UCLK: Clock frequency selected by the UAnCTL1.UAnCKS3 to
UAnCTL1.UAnCKS0 bits