Datasheet

V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
R01UH0015EJ0300 Rev.3.00 Page 476 of 870
Sep 30, 2010
(2) UARTAn control register 1 (UAnCTL1)
The UAnCTL1 register is an 8-bit register that selects the UARTAn base clock.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
Caution Clear the UAnCTL0.UAnPWR bit to 0 before rewriting the UAnCTL1 register.
0UAnCTL1
(n = 0 to 2)
0 0 0 UAnCKS3 UAnCKS2 UAnCKS1 UAnCKS0
654321
After reset: 00H R/W Address: UA0CTL1 FFFFFA01H, UA1CTL1 FFFFFA11H,
UA2CTL1 FFFFFA21H
7 0
f XX
f XX /2
f
XX /4
f
XX /8
f
XX /16
f
XX /32
f
XX /64
f
XX /128
f
XX /256
f
XX /512
f
XX /1,024
External clock
Note
(ASCKA0 pin)
Setting prohibited
UAnCKS2
0
0
0
0
1
1
1
1
0
0
0
0
UAnCKS3
0
0
0
0
0
0
0
0
1
1
1
1
Base clock (f
UCLK ) selectionUAnCKS1
0
0
1
1
0
0
1
1
0
0
1
1
UAnCKS0
0
1
0
1
0
1
0
1
0
1
0
1
Other than above
Note Only UARTA0 is valid; setting UARTA1 and UARTA2 is prohibited.
Remark f
XX: Main clock frequency