Datasheet

V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
R01UH0015EJ0300 Rev.3.00 Page 475 of 870
Sep 30, 2010
15.7 Dedicated Baud Rate Generator
The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter, and
generates a serial clock during transmission and reception with UARTAn. Regarding the serial clock, a dedicated baud
rate generator output can be selected for each channel.
There is an 8-bit counter for transmission and another one for reception.
(1) Baud rate generator configuration
Figure 15-16. Configuration of Baud Rate Generator
fUCLK
Selector
UAnPWR
8-bit counter
Match detector Baud rate
UAnCTL2:
UAnBRS7 to UAnBRS0
1/2
UAnPWR, UAnTXEn bits (or UAnRXE bit)
UAnCTL1:
UAnCKS3 to UAnCKS0
fXX
fXX/2
fXX/4
f
XX/8
fXX/16
fXX/32
fXX/64
f
XX/128
fXX/256
fXX/512
f
XX/1024
ASCKA0
Note
Note Only UARTA0 is valid; setting UARTA1 and UARTA2 is prohibited.
Remarks 1. n = 0 to 2
2. f
XX: Main clock frequency
f
UCLK: Base clock frequency
(a) Base clock
When the UAnCTL0.UAnPWR bit is 1, the clock selected by the UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0
bits is supplied to the 8-bit counter. This clock is called the base clock (f
UCLK).
(b) Serial clock generation
A serial clock can be generated by setting the UAnCTL1 register and the UAnCTL2 register (n = 0 to 2).
The base clock is selected by UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits.
The frequency division value for the 8-bit counter can be set using the UAnCTL2.UAnBRS7 to
UAnCTL2.UAnBRS0 bits.