Datasheet

V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
R01UH0015EJ0300 Rev.3.00 Page 474 of 870
Sep 30, 2010
15.6.10 Receive data noise filter
This filter samples the RXDAn pin using the base clock of the prescaler output.
When the same sampling value is read twice, the match detector output changes and the RXDAn signal is sampled as
the input data. Therefore, data not exceeding 1 clock width is judged to be noise and is not delivered to the internal circuit
(see Figure 15-15). See 15.7 (1) (a) Base clock regarding the base clock.
Moreover, since the circuit is as shown in Figure 15-14, the processing that goes on within the receive operation is
delayed by 3 clocks in relation to the external signal status.
Figure 15-14. Noise Filter Circuit
Match
detector
In
Base clock (f
UCLK)
RXDAn
QIn
LD_EN
Q Internal signal C
Internal signal B
In Q
Internal signal A
Figure 15-15. Timing of RXDAn Signal Judged as Noise
Internal signal B
Base clock
RXDAn (input)
Internal signal C
Mismatch
(judged as noise)
Internal signal A
Mismatch
(judged as noise)
Match Match
<R>
<R>