Datasheet

V850ES/JG3 CHAPTER 3 CPU FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 33 of 870
Sep 30, 2010
(6) Exception/debug trap status saving registers (DBPC and DBPSW)
DBPC and DBPSW are exception/debug trap status registers.
If an exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those
of the program status word (PSW) are saved to DBPSW.
The contents to be saved to DBPC are the address of the instruction next to the one that is being executed when
an exception trap or debug trap occurs.
The current contents of the PSW are saved to DBPSW.
These registers can be read or written only during the interval between the execution of the DBTRAP instruction or
illegal opcode and the DBRET instruction.
Bits 31 to 26 of DBPC and bits 31 to 8 of DBPSW are reserved for future function expansion (fixed to 0).
The value of DBPC is restored to the PC and the value of DBPSW to the PSW by the DBRET instruction.
31 0
DBPC
(Saved PC contents) 00
Default value
0xxxxxxxH
(x: Undefined)
26 25
0 0 0 0
31 0
DBPSW
(Saved PSW
contents)
00
Default value
000000xxH
(x: Undefined)
87
0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0
(7) CALLT base pointer (CTBP)
The CALLT base pointer (CTBP) is used to specify a table address or generate a target address (bit 0 is fixed to 0).
Bits 31 to 26 of this register are reserved for future function expansion (fixed to 0).
31 0
CTBP
(Base address) 00
Default value
0xxxxxxxH
(x: Undefined)
26 25
0 0 0 0 0