Datasheet

V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
R01UH0015EJ0300 Rev.3.00 Page 470 of 870
Sep 30, 2010
15.6.7 UART reception
The reception wait status is set by setting the UAnCTL0.UAnPWR bit to 1 and then setting the UAnCTL0.UAnRXE bit to
1. In the reception wait status, the RXDAn pin is monitored and start bit detection is performed.
Start bit detection is performed using a two-step detection routine.
First the rising edge of the RXDAn pin is detected and sampling is started at the falling edge. The start bit is recognized
if the RXDAn pin is low level at the start bit sampling point. After a start bit has been recognized, the receive operation
starts, and serial data is saved to the UARTAn receive shift register according to the set baud rate.
When the reception complete interrupt request signal (INTUAnR) is output upon reception of the stop bit, the data of the
UARTAn receive shift register is written to the UAnRX register. However, if an overrun error (UAnSTR.UAnOVE bit) occurs,
the receive data at this time is not written to the UAnRX register and is discarded.
Even if a parity error (UAnSTR.UAnPE bit) or a framing error (UAnSTR.UAnFE bit) occurs during reception, reception
continues until the reception position of the first stop bit, and INTUAnR is output following reception completion.
Figure 15-13. UART Reception
Start
bit
D0 D1 D2 D3 D4 D5 D6 D7
Parity
bit
Stop
bit
INTUAnR
RXDAn
UAnRX
Cautions 1. Be sure to read the UAnRX register even when a reception error occurs. If the UAnRX register is
not read, an overrun error occurs during reception of the next data, and reception errors continue
occurring indefinitely.
2. The operation during reception is performed assuming that there is only one stop bit. A second
stop bit is ignored.
3. When reception is completed, read the UAnRX register after the reception complete interrupt
request signal (INTUAnR) has been generated, and clear the UAnPWR or UAnRXE bit to 0. If the
UAnPWR or UAnRXE bit is cleared to 0 before the INTUAnR signal is generated, the read value of
the UAnRX register cannot be guaranteed.
4. If receive completion processing (INTUAnR signal generation) of UARTAn and the UAnPWR bit = 0
or UAnRXE bit = 0 conflict, the INTUAnR signal may be generated in spite of these being no data
stored in the UAnRX register.
To complete reception without waiting INTUAnR signal generation, be sure to clear (0) the
interrupt request flag (UAnRIF) of the UAnRIC register, after setting (1) the interrupt mask flag
(UAnRMK) of the interrupt control register (UAnRIC) and then set (1) the UAnPWR bit = 0 or
UAnRXE bit = 0.