Datasheet

V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
R01UH0015EJ0300 Rev.3.00 Page 465 of 870
Sep 30, 2010
15.6.4 SBF reception
The reception enabled status is achieved by setting the UAnCTL0.UAnPWR bit to 1 and then setting the
UAnCTL0.UAnRXE bit to 1.
The SBF reception wait status is set by setting the SBF reception trigger (UAnOPT0.UAnSTR bit) to 1.
In the SBF reception wait status, similarly to the UART reception wait status, the RXDAn pin is monitored and start bit
detection is performed.
Following detection of the start bit, reception is started and the internal counter counts up according to the set baud rate.
When a stop bit is received, if the SBF width is 11 or more bits, normal processing is judged and a reception complete
interrupt request signal (INTUAnR) is output. The UAnOPT0.UAnSRF bit is automatically cleared and SBF reception ends.
Error detection for the UAnSTR.UAnOVE, UAnSTR.UAnPE, and UAnSTR.UAnFE bits is suppressed and UART
communication error detection processing is not performed. Moreover, data transfer of the UARTAn reception shift register
and UAnRX register is not performed and FFH, the initial value, is held. If the SBF width is 10 or fewer bits, reception is
terminated as error processing without outputting an interrupt, and the SBF reception mode is returned to. The UAnSRF
bit is not cleared at this time.
Cautions 1. If SBF is transmitted during a data reception, a framing error occurs.
2. Do not set the SBF reception trigger bit (UAnSRT) and SBF transmission trigger bit (UAnSTT) to 1
during an SBF reception (UAnSRF = 1).
Figure 15-9. SBF Reception (1/2)
(a) Normal SBF reception (detection of stop bit in more than 10.5 bits)
UAnSRF
RXDAn 123456
11.5
7 8 9 10 11
INTUAnR
interrupt