Datasheet

V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
R01UH0015EJ0300 Rev.3.00 Page 460 of 870
Sep 30, 2010
15.6 Operation
15.6.1 Data format
Full-duplex serial data reception and transmission is performed.
As shown in Figure 15-5, one data frame of transmit/receive data consists of a start bit, character bits, parity bit, and
stop bit(s).
Specification of the character bit length within 1 data frame, parity selection, specification of the stop bit length, and
specification of MSB/LSB-first transfer are performed using the UAnCTL0 register.
Moreover, control of UART output/inverted output for the TXDAn bit is performed using the UAnOPT0.UAnTDL bit.
• Start bit..................1 bit
• Character bits ........7 bits/8 bits
• Parity bit ................Even parity/odd parity/0 parity/no parity
• Stop bit ..................1 bit/2 bits