Datasheet

V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
R01UH0015EJ0300 Rev.3.00 Page 459 of 870
Sep 30, 2010
15.5 Interrupt Request Signals
The following two interrupt request signals are generated from UARTAn.
• Reception complete interrupt request signal (INTUAnR)
• Transmission enable interrupt request signal (INTUAnT)
The default priority for these two interrupt request signals is reception complete interrupt request signal then
transmission enable interrupt request signal.
Table 15-2. Interrupts and Their Default Priorities
Interrupt Priority
Reception complete High
Transmission enable Low
(1) Reception complete interrupt request signal (INTUAnR)
A reception complete interrupt request signal is output when data is shifted into the receive shift register and
transferred to the UAnRX register in the reception enabled status.
A reception complete interrupt request signal is also output when a reception error occurs. Therefore, when a
reception complete interrupt request signal is acknowledged and the data is read, read the UAnSTR register and
check that the reception result is not an error.
No reception complete interrupt request signal is generated in the reception disabled status.
(2) Transmission enable interrupt request signal (INTUAnT)
If transmit data is transferred from the UAnTX register to the UARTAn transmit shift register with transmission
enabled, the transmission enable interrupt request signal is generated.