Datasheet

V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
R01UH0015EJ0300 Rev.3.00 Page 458 of 870
Sep 30, 2010
(6) UARTAn receive data register (UAnRX)
The UAnRX register is an 8-bit buffer register that stores parallel data converted by the receive shift register.
The data stored in the receive shift register is transferred to the UAnRX register upon completion of reception of 1
byte of data.
During LSB-first reception when the data length has been specified as 7 bits, the receive data is transferred to bits
6 to 0 of the UAnRX register and the MSB always becomes 0. During MSB-first reception, the receive data is
transferred to bits 7 to 1 of the UAnRX register and the LSB always becomes 0.
When an overrun error (UAnOVE) occurs, the receive data at this time is not transferred to the UAnRX register and
is discarded.
This register is read-only, in 8-bit units.
In addition to reset input, the UAnRX register can be set to FFH by clearing the UAnCTL0.UAnPWR bit to 0.
UAnRX
(n = 0 to 2)
654321
After reset: FFH R Address:
UA0RX FFFFFA06H, UA1RX FFFFFA16H,
UA2RX FFFFFA26H
7 0
(7) UARTAn transmit data register (UAnTX)
The UAnTX register is an 8-bit register used to set transmit data.
This register can be read or written in 8-bit units.
Reset sets this register to FFH.
UAnTX
(n = 0 to 2)
654321
After reset: FFH R/W Address: UA0TX FFFFFA07H, UA1TX FFFFFA17H,
UA2TX FFFFFA27H
7 0