Datasheet

V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
R01UH0015EJ0300 Rev.3.00 Page 456 of 870
Sep 30, 2010
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UAnSLS2
1
1
1
0
0
0
0
1
UAnSLS1
0
1
1
0
0
1
1
0
UAnSLS0
1
0
1
0
1
0
1
0
13-bit output (reset value)
14-bit output
15-bit output
16-bit output
17-bit output
18-bit output
19-bit output
20-bit output
SBF transmit length selection
• The output level of the TXDAn pin can be inverted using the UAnTDL bit.
• This register can be set when the UAnPWR bit = 0 or when the UAnTXE bit = 0.
This register can be set when the UAnPWR bit = 0 or when the UAnTXE bit = 0.
Normal output of transfer data
Inverted output of transfer data
UAnTDL
0
1
Transmit data level bit
• The input level of the RXDAn pin can be inverted using the UAnRDL bit.
• This register can be set when the UAnPWR bit = 0 or the UAnRXE bit = 0.
Normal input of transfer data
Inverted input of transfer data
UAnRDL
0
1
Receive data level bit
(5) UARTAn status register (UAnSTR)
The UAnSTR register is an 8-bit register that displays the UARTAn transfer status and reception error contents.
This register can be read or written in 8-bit or 1-bit units, but the UAnTSF bit is a read-only bit, while the UAnPE,
UAnFE, and UAnOVE bits can both be read and written. However, these bits can only be cleared by writing 0; they
cannot be set by writing 1 (even if 1 is written to them, the value is retained).
The initialization conditions are shown below.
Register/Bit Initialization Conditions
UAnSTR register
• Reset
• UAnCTL0.UAnPWR = 0
UAnTSF bit • UAnCTL0.UAnTXE = 0
UAnPE, UAnFE, UAnOVE bits
• 0 write
• UAnCTL0.UAnRXE = 0