Datasheet

V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
R01UH0015EJ0300 Rev.3.00 Page 455 of 870
Sep 30, 2010
(2) UARTAn control register 1 (UAnCTL1)
For details, see 15.7 (2) UARTAn control register 1 (UAnCTL1).
(3) UARTAn control register 2 (UAnCTL2)
For details, see 15.7 (3) UARTAn control register 2 (UAnCTL2).
(4) UARTAn option control register 0 (UAnOPT0)
The UAnOPT0 register is an 8-bit register that controls the serial transfer operation of the UARTAn register.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 14H.
(1/2)
UAnSRF
When the UAnCTL0.UAnPWR bit = UAnCTL0.UAnRXE bit = 0 are set.
Also upon normal end of SBF reception.
During SBF reception
UAnSRF
0
1
SBF reception flag
UAnOPT0
(n = 0 to 2)
UAnSRT UAnSTT UAnSLS2 UAnSLS1 UAnSLS0 UAnTDL UAnRDL
654321
After reset: 14H R/W Address: UA0OPT0 FFFFFA03H, UA1OPT0 FFFFFA13H,
UA2OPT0 FFFFFA23H
SBF reception trigger
UAnSRT
0
1
SBF reception trigger
• SBF (Sync Break Field) reception is judged during LIN communication.
• The UAnSRF bit is held at 1 when an SBF reception error occurs, and then SBF
reception is started again.
• UAnSRF bit is a read-only bit.
• This is the SBF reception trigger bit during LIN communication, and when read,
“0” is always read. For SBF reception, set the UAnSRT bit (to 1) to enable SBF
reception.
• Set the UAnSRT bit after setting the UAnPWR bit = UAnRXE bit = 1.
• This is the SBF transmission trigger bit during LIN communication, and when read,
“0” is always read.
• Set the UAnSTT bit after setting the UAnPWR bit = UAnTXE bit = 1.
SBF transmission trigger
UAnSTT
0
1
SBF transmission trigger
<7> 0
−
−
Caution Do not set the UAnSRT and UAnSTT bits (to 1) during SBF reception (UAnSRF bit = 1).