Datasheet

V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
R01UH0015EJ0300 Rev.3.00 Page 454 of 870
Sep 30, 2010
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7 bits
8 bits
UAnCL
0
1
Specification of data character length of 1 frame of transmit/receive data
• This register can be rewritten only when the UAnPWR bit = 0 or the UAnTXE bit =
the UAnRXE bit = 0.
• When transmission and reception are performed in the LIN format, set the UAnCL
bit to 1.
1 bit
2 bits
UAnSL
0
1
Specification of length of stop bit for transmit data
This register can be rewritten only when the UAnPWR bit = 0 or the UAnTXE bit =
the UAnRXE bit = 0.
• This register is rewritten only when the UAnPWR bit = 0 or the UAnTXE bit = the
UAnRXE bit = 0.
•
If “Reception with 0 parity” is selected during reception, a parity check is not performed.
Therefore, the UAnSTR.UAnPE bit is not set.
• When transmission and reception are performed in the LIN format, clear the
UAnPS1 and UAnPS0 bits to 00.
No parity output
0 parity output
Odd parity output
Even parity output
Reception with no parity
Reception with 0 parity
Odd parity check
Even parity check
UAnPS1
0
0
1
1
Parity selection during transmission Parity selection during reception
UAnPS0
0
1
0
1
MSB-first transfer
LSB-first transfer
UAnDIR
0
1
Transfer direction selection
• This register can be rewritten only when the UAnPWR bit = 0 or the UAnTXE bit =
the UAnRXE bit = 0.
• When transmission and reception are performed in the LIN format, set the UAnDIR
bit to 1.
Remark For details of parity, see 15.6.9 Parity types and operations.