Datasheet

V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
R01UH0015EJ0300 Rev.3.00 Page 451 of 870
Sep 30, 2010
15.3 Configuration
The block diagram of the UARTAn is shown below.
Figure 15-4. Block Diagram of Asynchronous Serial Interface An
Internal bus
Internal bus
UAnOPT0
UAnCTL0
UAnSTR
UAnCTL1
UAnCTL2
Receive
shift register
UAnRX
Filter
Selector
UAnTX
Transmit
shift register
Transmission
controller
Reception
controller
Selector
Baud rate
generator
Baud rate
generator
INTUAnR
INTUAnT
TXDAn
RXDAn
f XX to f XX /2
10
ASCKA0
Note
Reception unit
Transmission
unit
Clock
selector
Note UARTA0 only
Remarks 1. n = 0 to 2
2. For the configuration of the baud rate generator, see Figure 15-16.
UARTAn includes the following hardware.
Table 15-1. Configuration of UARTAn
Item Configuration
Registers UARTAn control register 0 (UAnCTL0)
UARTAn control register 1 (UAnCTL1)
UARTAn control register 2 (UAnCTL2)
UARTAn option control register 0 (UAnOPT0)
UARTAn status register (UAnSTR)
UARTAn receive shift register
UARTAn receive data register (UAnRX)
UARTAn transmit shift register
UARTAn transmit data register (UAnTX)